Microsemi Corporation has announced it has achieved National Institute of Standards and Technology (NIST) algorithmic certification on its U.S.-developed EnforcIT Cryptography Suite of National Security Agency (NSA) Suite B algorithms.The EnforcIT Cryptography Suite contains intellectual property (IP) cores for the Advanced Encryption Standard (AES), the XTS-AES Tweakable Block Cipher, Elliptic Curve Cryptography (ECC), and the Secure Hashing Algorithm (SHA-2) with HMAC.
These cryptography cores support multiple key sizes and block cipher modes. In addition, the highly configurable cores address security, area and throughput needs on all standard SRAM FPGAs, flash-based FPGAs and ASICs.
“Microsemi has a long track record of providing cryptography products that deliver outstanding security and value to the United States government and Department of Defense,” said Charlie Leader, vice president at Microsemi. “Earning this important certification for our EnforcIT Cryptography Suite is yet another step forward in our quest to provide increasingly secure, industry-qualified solutions that meet or exceed our customers” critical data needs.”
Microsemi”s EnforcIT Cryptography Suite includes many of the key sizes, operating modes and features expected in a full NSA Suite B cryptography algorithmic implementation. Specifically, the AES core provides 128, 192 and 256-bit key size support in CBC, CFB, OFB and CTR block cipher modes. The ECC core is an elliptic curve arithmetic unit with support for elliptic curve digital signature algorithms (ECDSA) on 256-bit prime fields (384 and 521-bit key sizes can be supported upon request). SHA-2 supports digest computation for 224, 256, 384 and 512-bit digest sizes with bit-length messages. HMAC supports any combination of SHA-2 algorithms, bit-length keys and messages. XTS-AES supports 128, 192 and 256-bit key sizes; whole block ciphering; and provides length-preserving encryption.
The EnforcIT Cryptography Suite is designed for flexibility in speed and security, and now provides higher assurance with NIST algorithmic certification. All IP cores are designed for low-risk integration into nearly all standard SRAM or flash-based FPGAs, and could be instantiated into an ASIC design. These and other Microsemi cryptography products including WhiteboxCRYPTO are designed and built in the U.S. in Microsemi”s facility located in Phoenix, Ariz. and in West Lafayette, Ind.