Speaking at the Globalpress Electronic Summit in Santa Cruz, Victor Peng, the company”s Senior Vice President of its Programmable Platform Group said that the new Vivado tools would not only speed up the design of programmable logic and I/O, but accelerate programmable systems integration and implementation into devices incorporating 3D stacked silicon interconnect technology, ARM processing systems, Analog Mixed Signal (AMS), and a significant percentage of semiconductor intellectual property (IP) cores.
According to Peng, “the design suite will provide a 4x boost to productivity and attacks the major bottlenecks in programmable systems integration and implementation. We believe it will drammatically boost customer productivity”
“Vivado tools are the culmination of work started by Xilinx engineers in 2008 in response to customers” needs for more productivity, faster time to market, and the ability to go beyond programmable logic to programmable systems integration,” said Peng. He added, “Essentially we started with a clean sheet.”
The tools have been beta tested with more than 100 customers and Alliance Program members over the past 12 months, including customers using the company”s stacked silicon interconnect-based Virtex-7 devices for extreme capacity and bandwidth.
The Vivado Design Suite provides an integrated design environment (IDE) with a completely new generation of system-to-IC level tools, all built on the backbone of a shared scalable data model and a common debug environment. It is also an open environment based on industry standards such as the AMBA4 AXI4 interconnect specification, IP-XACT IP packaging metadata, the Tool Command Language (Tcl), Synopsys Design Constraints (SDC) and others that facilitate design flows tailored to the user”s needs. Xilinx architected Vivado tools to enable the combination of all types of programmable technologies and scale up to 100-million-ASIC equivalent gate designs.
To address integration bottlenecks, the Vivado IDE includes electronic system level (ESL) design tools for rapidly synthesizing and verifying C based algorithmic IP; standards based packaging of both algorithmic and RTL IP for reuse; standards based IP stitching and systems integration of all types of system building blocks; and the verification of blocks and systems with 3X faster simulation, while hardware co-simulation provides 100X more performance.
Vivado tools include a hierarchical device editor and floor planner, a 3-15X faster logic synthesis tool with industry leading support for SystemVerilog, and a 4X faster, more deterministic place and route engine that uses analytics to minimize a “cost” function of multiple variables such as timing, wire length and routing congestion. In addition, incremental flows allow for engineering change order (ECO) induced changes to be quickly processed by only re-implementing a small part of the design, while preserving performance.
Finally, leveraging the new shared scalable data model, the tools provide power, timing and area estimates at every stage of the design flow, enabling up front analysis and then optimization with integrated capabilities such as automated clock gating.
“The combination of the Vivado Design Suite and the Virtex-7 2000T FPGA has created a paradigm shift in the programmable logic industry. Vivado has enabled Broadcom to design with the industry”s highest capacity FPGA without any manual floorplanning or partitioning,” said Paul Rolfe, Manager, Hardware Development Engineering, Broadcom Europe.
The Vivado Design Suite version 2012.1 is available as part of an early access program. Public access will commence with version 2012.2 early this summer, followed by WebPACK availability and Zynq-7000 Extensible Processing Platform support later in the year.
ISE Design Suite Edition customers with current support will be provided the new Vivado Design Suite Editions in addition to ISE at no additional cost. The ISE Design Suite will continue to be supported by Xilinx for customers targeting 7 series devices and prior generations.